- Developed PII privacy and security workflows using frozen Qwen 3.5 and Llama 3.1 models, achieving a 3% F1 score improvement over ModernBERT by disabling causal masking to capture full bidirectional context.
- Developing probe models on top of decoder hidden states to detect PII at the token level.
- Working on cost optimization and model routing for Claude Code by classifying session intent and routing sessions to the appropriate Claude model.
- Integrating vLLM with sparse autoencoders (SAEs) to capture token-level signals during generation in a single pass.
About
I am a Ph.D. candidate in the Department of Computer Science and Engineering at the University of South Florida, advised by Dr. Mehran Mozaffari Kermani and co-advised by Dr. Rouzbeh Behnia.
My research is in machine learning security and post-quantum cryptography. I design algorithm-level error-detection and fault-attack countermeasures for PQC schemes (Kyber, Dilithium) and classical ECC/elliptic-curve hardware, and study side-channel and fault-injection resilience for cryptographic and DNN inference pipelines. On the ML side, I work on privacy-preserving training (differentially private federated learning) and adversarial robustness (evasion attacks against RAG retrieval). This work won a Best Paper Award at IEEE S&P 2025 Workshops.
I'm currently an ML Research Engineer Intern at RealmLabs, building production PII-detection and model-routing systems for Claude Code — bridging side-channel and adversarial-ML research with real-world ML security engineering.
Experience
- Designed a human-in-the-loop, differentially private federated learning framework for fine-tuning LLMs (BERT) on memory-constrained devices, solving the fixed-memory limitation of existing DP mechanisms; won Best Paper Award at IEEE S&P 2025 Workshops (HMI-SA).
- Built MAED, an algorithm-level runtime error-detection framework using mathematical identities to catch fault-injection attacks and hardware faults on DNN activation functions (ReLU, sigmoid, tanh), hardening embedded ML inference pipelines against adversarial and natural faults.
- Designed algorithm-level error detection and side-channel/fault-attack countermeasures for NIST-standardized post-quantum cryptosystems (CRYSTALS-Kyber, Dilithium) and classical public-key schemes (ECC/ECSM, Montgomery Ladder), benchmarked on FPGAs, ARM, and embedded Linux; published in IEEE TVLSI, IEEE TCAD, and ACM TECS.
- Authored 10+ peer-reviewed papers spanning ML security, privacy-preserving AI, and hardware security under an NSF-funded research program (Award #1801488); serve as a peer reviewer for IEEE TVLSI, TCAS-I, and ACM TECS.
- Teaching assistant for Deep Learning in Computer Vision, Cryptography, Operating Systems, Computer Architecture, Network Lab, and System Design.
- Designed and implemented cloud-native AI workflows combining LLMs, RAG, and multi-agent orchestration.
- Built an AWS-based ETL pipeline using Lambda, Glue, and S3 to process laboratory nutrient data for crop recommendation models, supporting nutrient recommendations tailored to various growth stages of corn and soybeans.
- Implemented an event-driven architecture utilizing Lambda functions, Step Functions, Event Bridge, SES, and API Gateway to promote loose coupling and scalability.
- Analyzed optimal floor levels for elevators at specific times to reduce passenger wait times using machine learning, such as logistic regression and KNN.
- Established a connection between Raspberry Pi embedded boards and elevators through the CAN bus protocol for real-time data transfer to a Linux-powered IoT system.
- Built ETL pipelines using Apache Airflow to extract, ingest, and load elevator traffic data to an OLAP store.
- Reduced passenger wait times by 27% across deployments in 100+ commercial buildings.
Education
Publications
- An Interactive Framework for Implementing Privacy-Preserving Federated Learning: Experiments on Large Language Models In 2025 IEEE Security and Privacy Workshops (SPW), San Francisco, CA, USA. Best Paper Award.
- Efficient Algorithm Level Error Detection for Number-Theoretic Transform Assessed on FPGAs ACM Transactions on Embedded Computing Systems, 2025.
- MAED: Mathematical Activation Error Detection for Mitigating Physical Fault Attacks in DNN Inference In submission.
- PUF-Kyber: Design of a PUF-Based Kyber Architecture Benchmarked on Diverse ARM Processors IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.
- Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 3, pp. 592-596, March 2024.
- PUF-Dilithium: Design of a PUF-Based Dilithium Architecture Benchmarked on ARM Processors ACM Transactions on Embedded Computing Systems, vol. 24, no. 2.
- Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder IEEE Transactions on Very Large Scale Integration (VLSI) Systems, early access, 2024.
- A P2P File Sharing Market Based on Blockchain and IPFS with Dispute Resolution Mechanism IEEE Int'l Conf. on Artificial Intelligence, Blockchain, and Internet of Things (AIBThings), Mount Pleasant, MI, pp. 1-5, 2023.
- [Preprint] Error Detection Schemes for τ NAF Conversion within Koblitz Curves Benchmarked on Various ARM Processors TechRxiv.
- [Preprint] Efficient Fault Detection Architectures for Modular Exponentiation Targeting Cryptographic Applications Benchmarked on FPGAs arXiv preprint arXiv:2402.18033
- [Preprint] Envisioning the Future of Cyber Security in Post-Quantum Era: A Survey on PQ Standardization, Applications, Challenges and Opportunities arXiv:2310.12037, 2023.
Projects
Human-in-the-loop framework for privacy-utility trade-off control in federated fine-tuning of BERT-based models using Flower, DP-SGD, and LoRA. Best Paper Award, IEEE S&P 2025 Workshops.
Algorithm-level error-detection methods using mathematical identities to catch fault-injection attacks and hardware faults on DNN activation functions (ReLU, sigmoid, tanh) for safety- and security-critical inference deployments.
Simulated fault-injection attacks on Kyber, Dilithium, and ECC, then proposed lightweight algorithm-level countermeasures with near-100% error detection, benchmarked on FPGAs and ARM.
Evasion attacks that perturb vector embeddings to degrade RAG retrieval quality, answer reliability, and downstream system accuracy.
Certifications
- AWS Certified Solutions Architect - Associate, Dec 2023
- Deep Neural Networks with PyTorch, Oct 2024
- Intro to Federated Learning, Oct 2024
- Artificial Intelligence Privacy and Convenience, Aug 2024
- Federated Fine-tuning of LLMs with Private Data, Aug 2024
- ETL and Data Pipelines with Shell, Airflow and Kafka, Jan 2024
- Divide and Conquer, Sorting and Searching, and Randomized Algorithms, Oct 2023
Service
- Conducted peer review for 21 manuscripts from IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Circuits and Systems I: Regular Papers, and ACM Transactions on Embedded Computing Systems.
- Mentor, Research Experiences for Undergraduates (REU) Program, Summer 2023, USF (NSF Award #2244488).
- Teaching Assistant, Graduate Operating Systems, Spring 2023, USF.
- Teaching Assistant, Cryptographic Hardware, Fall 2022 and 2023, USF.
- Teaching Assistant, System Design Lab, Spring 2023 and 2024, USF.
- Teaching Assistant, Computer Organization, Spring 2022 and 2024, USF.